Make A Shift Register Using D Flip Flops Verilog

Introduction

A shift register using D flip flops Verilog is a fundamental building block in digital design that enables serial data storage, data transfer, and timing control. Whether you are implementing a UART receiver, constructing a finite‑state machine, or building a simple LED chaser on an FPGA, mastering how to describe a shift register in Verilog is essential. This article walks you through the theory, the Verilog coding style, simulation, and synthesis tips needed to create a reliable, parameterizable shift register that targets both ASIC and FPGA technologies.

Understanding Shift Registers

A shift register is a cascade of flip‑flops where the output of one flip‑flop feeds the data input of the next. On each clock edge, the stored bits move one position toward the output (or input) side, hence the name “shift.”

• Serial‑In Parallel‑Out (SIPO) – data enters serially and becomes available on all outputs simultaneously.
• Parallel‑In Serial‑Out (PISO) – parallel data is loaded at once and then shifted out serially.
• Universal Shift Register – combines SIPO, PISO, and bidirectional shifting capabilities.

The core element in every variant is the D flip‑flop, which captures the value present at its D input on the rising (or falling) clock edge and holds it until the next edge.

Types of Shift Registers Implemented with D Flip‑Flops

For the purpose of this tutorial we will focus on a parameterizable SIPO shift register because it showcases the basic D‑flip‑flop chain and is easily extensible to other configurations.

Designing a Shift Register with D Flip‑Flops in Verilog

1. Define the Module Interface

    parameter WIDTH = 8          // Number of stages) (
    input  wire               clk,   // Clock
    input  wire               rst_n, // Asynchronous active‑low reset
    input  wire               ser_in,// Serial data input
    output wire [WIDTH-1:0]   parallel_out // Parallel output
);

• Parameter WIDTH lets the designer reuse the same code for 4‑bit, 8‑bit, 16‑bit, etc., registers without rewriting the logic.
• Active‑low reset (rst_n) is a common FPGA convention; it clears all flip‑flops to a known state.

2. Declare Internal Storage

We use a reg vector to represent the chain of D flip‑flops. Each bit of the vector corresponds to one flip‑flop’s Q output.

reg [WIDTH-1:0] shift_reg;

3. Describe the Flip‑Flop Behavior

A single always @(posedge clk or negedge rst_n) block infers a set of D flip‑flops with synchronous data capture and asynchronous reset.

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        shift_reg <= {WIDTH{1'b0}}; // Reset all bits to 0
    end else begin
        // Shift left: new serial input becomes LSB, previous bits move toward MSB
        shift_reg <= {shift_reg[WIDTH-2:0], ser_in};
    end
end

• The concatenation {shift_reg[WIDTH-2:0], ser_in} implements the shift operation.
• Using non‑blocking assignments (<=) ensures that all flip‑flops update simultaneously, matching hardware behavior.

4. Assign the Output The parallel output is simply the current content of the shift register.

assign parallel_out = shift_reg;

5. Complete Module

Putting everything together:

module sipo_shift_reg #(
    parameter WIDTH = 8
) (
    input  wire               clk,
    input  wire               rst_n,
    input  wire               ser_in,
    output wire [WIDTH-1:0]   parallel_out);

    reg [WIDTH-1:0] shift_reg;

    always @(posedge clk or negedge rst_n) begin        if (!rst_n) begin
            shift_reg <= {WIDTH{1'b0}};
        end else begin
            shift_reg <= {shift_reg[WIDTH-2:0], ser_in};
        end
    end

    assign parallel_out = shift_reg;

endmodule

Step‑by‑Step Implementation Guide

1. Create a new Verilog file (e.g., sipo_shift_reg.v) and paste the module above.

2. Choose a width that matches your design. For a UART receiver you might set WIDTH = 10 (start bit + 8 data + stop bit).

3. Instantiate the module in a top‑level testbench or system design:

   sipo_shift_reg #(.WIDTH(8)) u_shift (
       .clk         (sys_clk),
       .rst_n       (sys_rst_n),
       .ser_in      (rx_data),
       .parallel_out (rx_parallel)
   );
   

4. Write a testbench to verify functionality (see next section).

5. Run simulation (e.g., with Icarus Verilog, VCS, or QuestaSim) to confirm that the serial data appears correctly on the parallel outputs after WIDTH clock cycles.

6. Synthesize for your target FPGA (Xilinx Vivado, Intel Quartus, Lattice Diamond) or ASIC flow. Check the resource report: you should see WIDTH flip‑flops and negligible combinational logic.

Simulation and Testbench A simple testbench stimulates the shift register with a known pattern